Semiconductor devices having a layer of semiconductor material disposed on an insulating substrate are generally known in the art. An example of such a device is a silicon-on-insulator (SOI) semiconductor device which includes a silicon island formed on the surface of an insulating material. When the insulating material is a sapphire substrate, the structure is known as a silicon-on-sapphire (SOS) semiconductor device. Metal-oxide-semiconductor (MOS) transistors or other active devices are formed in and on the silicon island. MOS/SOI transistors generally have higher speed and improved radiation hardness in comparison with MOS transistors formed in bulk silicon.
MOS/SOI transistors are conventionally fabricated by first forming an island of semiconductor material, such as single-crystalline silicon, on the surface of an insulating substrate, such as sapphire. The silicon island is generally doped to have a first conductivity type. A gate oxide layer and a gate electrode are then formed on the island. Source and drain regions of a second conductivity type are formed in the silicon island using conventional ion implantation techniques. During the implantation step, the gate electrode acts as a masking layer so that self-aligned source and drain regions are formed in the silicon island. Then, the device is completed using conventional MOS processing techniques.
When fabricating complementary metal-oxide-semiconductor (CMOS) devices in a common island of semiconductor material, it is advantageous to extend the source and drain regions to the insulating substrate so as to avoid a large leakage current between the drain of the P-channel transistor and the source of the N-channel transistor. There can also be leakage between the drain of the N-channel transistor and the source of the P-channel transistor. J. Ohno in U.S. Pat. No. 4,507,846 entitled "Method For Making Complementary MOS Semiconductor Devices," issued Apr. 2, 1985, has addressed this problem by disclosing a method of extending the source and drain regions to the insulating substrate. In this process, a portion of the semiconductor layer between the gate electrodes is removed before the source and drains regions are formed. U.S. Pat. No. 4,507,846 also describes another process for extending the source and drain regions to the insulating substrate by using an additional set of photolithography and ion implantation steps for each MOS transistor.
Even when a single MOS transistor is formed in a single island of semiconductor material, it is desirable to extend the source and drain regions to the insulating substrate. If the source and drain regions do not reach the insulating substrate, the large junction areas form high source and drain capacitance with the body of the channel region. This high source and drain capacitance reduces the speed of the device.
When fabricating MOS/SOI devices, it is desirable to use silicon islands which have a thickness of about 5500 .ANG. or larger so that good quality heteroepitaxial silicon is present in the channel region. However, very high implant energies are needed in the conventional fabrication process to extend the self-aligned source and drain regions to the insulating substrate. When using these implant energies, the dopant ions can pass through the gate electrode, which is acting as a mask, and damage the underlying gate oxide. As discussed in the article by R. K. Smeltzer, entitled "Trap Creation In Channel Oxides Due To Ion Penetration Of Polycrystalline Silicon," Applied Physics Letter, 41(9), Nov. 1, 1982, pp. 849-851, the implanted ions produce a large concentration of hole traps in the gate oxide. These traps cause a very large shift in the threshold voltage of the MOS device. Thus, it would be desirable to fabricate MOS/SOI semiconductor devices in a thick island of semiconductor material, e.g. greater than about 5500 .ANG., with the source and drain regions extending to insulating substrate such that damage to the gate oxide is minimized during the implantation process.